A method for adjusting parameters of an integrated circuit, and, more particularly, a method for adjusting power dissipation in a metal oxide semiconductor integrated circuit after a prototype design has been completed.
Modern electronic circuits and systems are built on the foundation of discrete semiconductor devices and integrated circuits. An integrated circuit consists of both active and passive elements formed on a silicon substrate. Metal layers are provided to interconnect the electrically isolated active and passive elements, defining particular logic and circuit functions.
A Metal Oxide Semiconductor (xe2x80x9cMOSxe2x80x9d) integrated circuit is one of the most popular type of integrated circuits in digital applications, where only an on-off transistor response is required. A particularly useful unit cell for the integrated circuit is a Complementary MOS (xe2x80x9cCMOSxe2x80x9d), which uses both n-channel and p-channel MOS field effect transistors (xe2x80x9cFETxe2x80x9d) on adjacent regions of the chip. CMOS is one of the most widely used unit cells for various integrated circuits. One of the advantages of using CMOS is that the standard dc power dissipation can be reduced to very small levels.
A gate array is an integrated circuit including an array of unit cells such as CMOS arranged regularly on a semiconductor substrate, wherein interconnections for connecting the unit cells have not yet been formed. Desired logic functions, such as NAND, NOR or AND logic circuits may be obtained by connecting unit cells of the gate arrays into a functional block. Metal and insulating layers are added over the gate array to provide the interconnections required to define the functional block, in accordance with customer""s orders.
While gate array architectures are standardized at the chip geometry level, it is advantageous to provide standardization at the logic or function level, as well. A design may be created for any logic function which may be needed, including logic circuits, flip-flops and arithmetic logic unit functions. The design is commonly termed a xe2x80x9ccellxe2x80x9d. A plurality of different cells may be stored in a cell library for use in the design of a chip.
Fabrication of a CMOS gate array based integrated circuit may be divided into two phases: unit transistor formation phase and personalization/customization phase. Unit transistors are fabricated according to an n-well or p-well CMOS process which includes the steps of forming a well, defining an active area, growing field oxide for isolating unit cells, growing a thin oxide over the active area to define a gate insulator, depositing a polysilicon layer over the gate insulator to form a gate electrode and doping the active area to form source and drain regions. An oxide layer covers the top of the unit cell and contact points for enabling connection of the diffusion regions with the metallization layers to be provided in the personalization phase, are formed by the selective etching of the points.
In the personalization phase, the unit cells are interconnected to form logic circuits and the logic circuits are interconnected to implement the functions required by the customer. Typically, a first metal layer is deposited over the oxide layer of the unit transistors, an insulating oxide layer is deposited over the first metal layer and a second metal layer is deposited over the insulating oxide layer.
Throughout the first and second phase of the fabrication process, each of the layers are deposited and patterned in a photolithographic process using a set of customized masks. Commonly, thirteen or more unique masks are needed to fabricate a typical MOS integrated circuit. The design and number of the masks have a significant impact on the time and cost of the fabrication process.
Before commencing full production, it is a common practice to fabricate a small number of prototype integrated chips for testing to verify whether the performance of the integrated circuits fabricated by a set of masks in a production process meets the customer""s performance specifications. Testing may be performed at the supplier""s or the customer""s lab in a real or simulated environment. Such testing may include wafer probing, device parametrics, logical testing and speed/performance testing. If testing indicates that certain parameters of the transistors, such as the power dissipation, need to be modified, the unit cells and the connections between them need to be redesigned by changing the dimensions of the transistors. However, as described above, transistors are complex, multilevel structures which are fabricated by application of a plurality of precisely aligned layers, some of which are interconnected, and a separate mask is required for each layer. A change in the dimensions of the transistors, therefore, requires redesign of most or all of the masks. This is a time consuming process adding additional cost to the fabrication process. Adjustment of the operating parameters of the transistors without redesigning most or all of the verified masks would be advantageous.
In accordance with one embodiment of the present invention, only one mask of the set of masks used in the fabrication process needs to be redesigned to change the power dissipation of the integrated circuit. That new mask replaces the original active area mask in the set of masks. In the new mask, the patterns for defining the active areas have a different size as compared to the patterns on the original active area mask, changing the channel width of the transistors. Since both the capacitive loading and the current flow in the channel of transistors contribute to the power dissipation of designed circuits, reducing the gate widths of the transistors by reducing the active areas reduces capacitive loading and the current flow, decreasing power dissipation. The active area around the original contacts should be maintained so that the positions of the contacts need not be changed. Consequently, the masks for defining the position of the contacts and the masks for defining the metallization layers need not be changed. Preferably, the contacts are positioned midway between the gates, to facilitate the reduction in the size of the active area. The power dissipation may be increased by increasing the size of the active areas.